For decades, we lived in the comfort of Moore’s law which directs an exponential increase of CPU speed: The CPU clock was going up exponentially to approximately 3 GHz which was reached in 2004, but since then the frequencies stagnate. Instead, manufacturers try to pack multiple cores into a chip but the doubling of CPU cores per processors bounces in turn against the memory wall. People started then vigorous experimentation with accelerators GPUs, FPGAs and embedded technology: This paper will follow an application-centric approach, by comparing the pros and cons of these two key computational accelerations with respect to performance, power, productivity and costs. GPUs being already frequently analysed in the literature, we will focus on FPGAs which seems to offer the potential for flexible acceleration of many workloads but however, still to become mainstream in commodity systems.

FPGA-based Acceleration
The integration of FPGA computing must meet the following challenges:

• Homogeneous exploitation (in their interaction with other computing technologies);
• Adaptation of the evolution of FPGA Technology
• Debugging, Power Consumption
• Reliability, Accessibility and Security

and could be implemented in one of the following modes:

• Discrete FPGA: Offload CPU-FPGA interaction through a standard PCIe/FSB/HyperTransport interface;
• Message Passing : Organization in a cluster of Networked FPGAs with APIs to support send/receive of messages;
• Integrated FPGA : Integration with coherent low-latency interconnect thus simplify the programming model by supporting virtual addressing. This strong integration mode enables new class of algorithms by providing full access to system memory.

Hardware/Software Architecture
This section describes the requirements and hardware architecture of an FPGA-enhanced computing system (Figure 1). In combination with the hardware aspect, a layered software access model for FPGA accelerators (Cf. Figure 2) is necessary to provide common and extensible methods for discovery, profiling, access, management of accelerator resources and access to the software stack at different layers to aid in debug, bring-up, and deployment. These Hw/Sw architectures are defined for a compute node and hence are suitable to a server. They have to be extended in accordance respectively with the interconnect fabric and associated programming models to be adapted to HPC systems.

Examples of application
In this section we illustrate the application of FPGA computing in 3 different domains:

• ASIC prototyping to support Sw execution
  Hardware modelling and execution represent the native mode of FPGA and hence it provides the best speedup within the inetrval [104,107] depending on the nature and size of the ASIC.
• Quantum computation illustrated by the simulation of a stabilizer circuit)
  The Class of quantum stabilizer circuits is characterized by the following features:
• N Qbits Pauli operators Pn :Tensor product of 1 qbit Pauli operators
• Stabilizer operation (state) : Stab(| Ψ Ψ >
• Stabilizers of | Ψ > form an Abelia n group
  The porting of this algorithm on a n Altera/ Arria10 FPGA provi des a 15X speedup
• Artificial Intelligence Acceleration of the AlexNet Neural Network : The porting of AlexNet 59 layers) onto an Arria10 using the programming model OpenCL provides speed ups of 20X and 80X respectively for the training and inference phases.

Conclusions
FPGA acceleration starts to be adopted in the mainstream computing thanks to the benefits on performance/consumption and increasing ease-of-use. However a lot of works are still to be done in order to support the evolution towards an adaptive-acceleration data center